Modern Computer Architecture and Organization

Modern Computer Architecture and Organization, by Jim Ledin. Published by Packt Publishing.

Home / Chapter 11 - The RISC-V Architecture and Instruction Set

Chapter 11 - The RISC-V Architecture and Instruction Set

This chapter introduces the exciting, relatively new RISC-V (pronounced risk five) processor architecture and its instruction set. RISC-V is a completely open source specification for a reduced instruction set processor. A complete user-mode (non-privileged) instruction set specification has been released, and several inexpensive hardware implementations of this architecture are currently available. Work is ongoing to develop specifications for a number of instruction set extensions to support general-purpose computing, high-performance computing, and embedded applications. Commercially available processors implement many of these developmental extensions.

The following topics will be covered in this chapter:

The RISC-V architecture and features
The RISC-V base instruction set
RISC-V extensions
64-bit RISC-V
Standard RISC-V configurations
RISC-V assembly language
Implementing RISC-V in a field-programmable gate array (FPGA)

After completing this chapter, you will understand the architecture and capabilities of the RISC-V processor and its optional extensions. You will have learned the basics of the RISC-V instruction set and will understand how RISC-V can be tailored to support a variety of computer architectures, from low-end embedded systems to warehouse-scale cloud server farms. You will also have learned how to implement a RISC-V processor in a low-cost FPGA board.

Chapter Files

hello_riscv.s is the RISC-V hello assembly language program.

full_adder.scala is the implementation of a full adder in the Chisel domain-specific language within Scala.

Answers to Exercises

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